Area optimized architecture and VLSI implementation of a multi-coder processor for the WTLS

被引：0

作者：

Selimis, G ^{[1
]}

Sklavos, N ^{[1
]}

Koufopavlou, O ^{[1
]}

机构：

[1] Univ Patras, Dept Elect & Comp Engn, Patras, Greece

来源：

PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The rapidly growth of the transmitted data amount, over wireless networks, has triggered special needs for compression, in an attempt for real-time communications. Wireless Transport Layer Security (WTLS) is the security layer for both Wireless Application Protocol and Open Mobile Alliance. In spite of the fact that a great number of ciphers have been specified in WTLS, the compression unit is optional. Compression in wireless portable devices is a sensitive issue due to the restricted resources environment. The composite compression encoders allocate area that system can not support. In this paper, an area-optimized multi-coder processor is proposed for the WTLS. The proposed system consists of three units and serves three different types of compression: speech (ADPCM). text (Huffman) and image (RLE). The proposed processor minimizes the area resources compared with other published works and has competitive performance.

引用

页码：1263 / 1266

页数：4