Impact of 3D Stacking on the TSV-induced Stress and the CMOS Characteristics

被引：0

作者：

Dote, Aki ^{[1
]}

Tashiro, Hiroko ^{[1
]}

Kitada, Hideki ^{[1
]}

Tadaki, Shinji ^{[1
]}

Miyahara, Shoichi ^{[1
]}

Sakuyama, Seiki ^{[1
]}

机构：

[1] Fujitsu Ltd, 10-1 Morinosato Wakamiya, Atsugi, Kanagawa 2430197, Japan

来源：

2017 IEEE 19TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC) | 2017年

关键词：

PERFORMANCE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigated the impact of the stress induced by 3D stacking structure and through-silicon vias (TSV) on characteristics of CMOS. The 3D stacking structure was found to induce considerably large stress on the Si substrate compared to stress induced by TSV. The change of CMOS characteristics was calculated using a simple method of device simulation. A considerably large shift of the drain current of p-MOS near the TSV was predicted and confirmed by the measurement. The effect of stress induced by the stacking structures was not negligible as well as the well-known effect by TSV and should be considered for the design of advanced 3D-LSI systems.

引用

页数：5

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