Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance

A associative-memory architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified by a 0.6-mum 2-poly 3-metal CMOS design with 32 rows and 128 columns, achieving <100 ns search times and 1.57-mm(2) integration area. The only previous work with linear-scaling search circuitry reports just static measurements (no dynamic search times) for a design with 16 rows and 12 columns, i.e., 20 times smaller complexity.