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- [1] BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding 2012 16TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2012, : 145 - 149
- [2] Optimization of memory-constrained hybrid BIST for testing core-based systems 2007 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS, 2007, : 71 - 77
- [3] Optimization of test accesses with a combined BIST and external test scheme IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2001, E84A (11): : 2731 - 2738
- [4] Hybrid BIST design for n-detection test using partially rotational scan IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2002, E85D (10): : 1490 - 1497
- [6] TEST TIME OPTIMIZATION BY REVISITING NOTES IN VLSI BIST TECHNIQUE 3C TECNOLOGIA, 2020, (SI): : 19 - 33
- [7] Optimization and implement technique for test generation in the design of BIST architecture ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 1650 - 1654
- [8] Test Time Minimization for Hybrid BIST of Core-Based Systems Journal of Computer Science and Technology, 2006, 21 : 907 - 912
- [10] A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS RESEARCH AND MECHATRONICS ENGINEERING, 2015, 121 : 354 - 357