A 2.5-GHz 860μW charge-recycling fractional-N frequency synthesizer in 130nm CMOS

被引：4

作者：

Park, Dongmin ^{[1
]}

Lee, Wojae ^{[1
]}

Jeon, Sehyung ^{[1
]}

Cho, ScongHwan ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Taejon 305701, South Korea

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

frequency synthesizer; fractional; PLL; low power; charge recycling;

D O I：

10.1109/VLSIC.2008.4585963

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1.2V 2.5GHz 860 mu W fractional-N synthesizer is implemented in 130nm CMOS. It employs charge recycling technique for implicit DC-DC conversion Without using any voltage regulators, and achieves -77dBc/Hz and -113.5dBc/Hz of phase noise at 100kHz and 1MHz offset, respectively. Self-biased divider and VCO enables robust operation of the proposed circuit.

引用

页码：88 / 89

页数：2