A digitally calibrated 64.3-66.2GHz phase-locked loop

被引：0
|
作者：
Tsai, Kun-Hung [1 ]
Wu, Jia-Hao
Liu, Shen-Iuan
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
来源：
2008 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, VOLS 1 AND 2 | 2008年
关键词：
phase-locked loop; frequency divider; digital calibration; CMOS; clock generator;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a 64-3-66.2GHz digitally calibrated phase-locked loop (PLL) is presented in 0.13 mu m CMOS technology. A digital calibration circuit is adopted to align the center operation frequency between the VCO and the divider. At 64.3GHz, the measured phase noise at 1MHz offset is 84.1dBc/Hz. The PLL consumes 72mW without output buffers from 1.2V supply.
引用
收藏
页码：275 / +
页数：2
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