A new fabric of reconfigurable FFT processor for high-speed and low-cost system

A high-speed reconfigurable FFT architecture based on FPGA is proposed in this paper. The system can be configured as 32, 64,128, 256, 512 and 1024-point FFT using simplified method to control. It has been synthesized in Xilinx Virtex2p FPGA and post-simulated. Compared with Xilinx FFT IP Core with the same function this FFT fabric proposed has saved almost 8%similar to 9% (equivalent gates) in resources consumption while increased nearly 61%similar to 25% in clock frequency and decreased 56 similar to 116 cycles or delays from first input data to the first result data, indicating high computing efficiency. On the other hand, power consumption is also slightly fewer than the IP Core's. The fabric we presented in this paper is suitable for use in digital signal process with high-speed and low-cost.