Arithmetic logic unit for weighted sum calculation with programmable logic cell array

In this article the design of the arithmetic logic unit with serial arithmetic procedure for weighted sum calculation and programmable logic cell array implementation is presented. This arithmetic logic unit is especially intended for adaptive FIR digital filter realization because all the coefficients of the digital filter can be changed simultaneously between two input samples. FIR digital filter with proposed arithmetic logic unit with serial arithmetic is shown in Fig. 3. It can be designed in the modular structure (Fig. 5) that allows the whole system to be expanded to any number of coefficients with minimal effort. The previous realizations of digital filters in programmable circuits were focused on reduction of the complexity of the hardware realization /5/. The idea that stands behind the serial arithmetic structure is the reduction of hardware implementation complexity. It is shown that the hardware complexity increases linearly with the number of coefficients used (Table 1 and Fig. 8). The FIR digital filter in the modular structure consists of N cells. One cell of the modular structure is elementary arithmetic block (Fig. 4) and consists of serial multiplier (Fig. 6), serial adder (Fig. 7) and FIFO register. The filter has been designed in the Xilinx ISE 6.1 environment. The basic units, serial multiplier, serial adder and FIFO register of digital filter structure is designed with VHDL. The Xilinx schematic editor was used for connections between basic units. The test application is made with FIR digital filter of 16 coefficients and a 16-bit quantization of input and output signal. The Xilinx FPGA circuit XC3S-400 is used for implementation of FIR digital filter structures with 8, 16, 32 and 64 taps. The 64 taps FIR digital filter occupy only 72% of input output blocks (IOB) and 78% of slices of the whole XC3S-400 circuit used for this application. At 71 MHz clock frequency a sample frequency of input-output signal of 4.4 MHz has been obtained. The processing of one output signal sample needs 16 clock pulses.