Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation

被引：30

作者：

Saint-Martin, J ^{[1
]}

Bournel, A ^{[1
]}

Dollfus, P ^{[1
]}

机构：

[1] Univ Paris 11, CNRS, UMR 8622, Inst Elect Fondamentale, F-91405 Orsay, France

来源：

SOLID-STATE ELECTRONICS | 2006年 / 50卷 / 01期

关键词：

SOI; MOSFET; Monte Carlo simulation;

D O I：

10.1016/j.sse.2005.10.043

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements than in single-gate MOSFET. Our results highlight that planar double-gate MOSFET is a good candidate to obtain high current drive per unit-width and low subthreshold leakage with aggressive delay time. Additionally, this device offers much better ability to high integration density than nonplanar devices as triple-gate or quadruple-gate MOSFETs. However, we show that source-drain regions have to be carefully scaled to optimize the trade off between access resistance and fringe capacitance. (c) 2005 Elsevier Ltd. All rights reserved.

引用

页码：94 / 101

页数：8

共 12 条

[1] Layout density analysis of FinFETs [J].

Anil, KG ;

Henson, K ;

Biesemans, S ;

Collaert, N .

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, :139-142

[2] Silicon nano-transistors for logic applications [J].

Chau, R ;

Boyanov, B ;

Doyle, B ;

Doczy, M ;

Datta, S ;

Hareland, S ;

Jin, B ;

Kavalieros, J ;

Metz, M .

PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, 2003, 19 (1-2) :1-5

[3] Multiple-gate SOI MOSFETs [J].

Colinge, JP .

SOLID-STATE ELECTRONICS, 2004, 48 (06) :897-905

[4] Si/Si1-xGex heterostructures: Electron transport and field-effect transistor operation using Monte Carlo simulation [J].

Dollfus, P .

JOURNAL OF APPLIED PHYSICS, 1997, 82 (08) :3911-3916

[5] Comparison of raised source/drain versus raised extension in ultra-thin body, fully-depleted-SOI, including effects of BEOL via capacitances [J].

Egley, JL ;

Vandooren, A ;

Winstead, B ;

Verret, E ;

Workman, C ;

White, B ;

Nguyen, BY .

SOLID-STATE ELECTRONICS, 2004, 48 (09) :1607-1612

[6] Requirements for ultra-thin-film devices and new materials for the CMOS roadmap [J].

Fenouillet-Beranger, C ;

Skotnicki, T ;

Monfray, S ;

Carriere, N ;

Boeuf, F .

SOLID-STATE ELECTRONICS, 2004, 48 (06) :961-967

[7]

Harrison S, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P449

[8]

KEITH S, 1997, P ESSDERC, P200

[9] Velocity distribution of electrons along the channel of nanoscale MOS transistors [J].

Mouis, M ;

Barraud, S .

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, :147-150

[10] On the ballistic transport in nanometer-scaled DG MOSFETs [J].

Saint Martin, M ;

Bournel, A ;

Dollfus, P .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (07) :1148-1155

← 1 2 →