Effects of floating-gate interference on NAND flash memory cell operation

被引：423

作者：

Lee, JD ^{[1
]}

Hur, SH ^{[1
]}

Choi, JD ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Semicond Res & Dev Ctr, Memory Business, Gyunggi Do 449711, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2002年 / 23卷 / 05期

关键词：

EPROM; floating-gate interference; MOS memory integrated circuits; semiconductor device modeling;

D O I：

10.1109/55.998871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V-T shift of a cell proportional to the V-T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-mum design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.

引用

页码：264 / 266

页数：3

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