Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

被引：7
作者：
Banerjee, Kallolini [1 ]
Biswas, Abhijit [1 ]
机构：
[1] Univ Calcutta, Inst Radio Phys & Elect, 92 Acharya Prafulla Chandra Rd, Kolkata 700009, India
来源：
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2020年 / 124卷
关键词：
Charge plasma CFinFET; Fall time; Frequency of oscillations; JL-FinFET; Logic performance; Ring oscillator; FIELD-EFFECT TRANSISTOR; CIRCUIT PERFORMANCE; GATE; RESISTANCE; REDUCTION; DESIGN; IMMUNE; DEVICE; MOSFET;
D O I：
10.1016/j.aeue.2020.153350
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption P-DC, rise t(r) and fall t(f) times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent junctionless (JL) CFinFET inverters. Obtained results are physically analyzed including quantum-mechanical effects. Furthermore, the oscillation frequency of a three-stage ring oscillator constructed with CPJL-CFinFETs is computed, and compared with their JL-CFinFET counterpart. Our findings reveal that while dissipating less OFF-state power, t(r) and t(f) of the proposed CPJL inverter exhibit significant reduction of similar to 73.92% and similar to 79.82%, respectively, relative to its equally sized JL inverter value at 10 nm technology node. Moreover, the oscillation frequency of a three-stage ring oscillator (RO) built with CPJL inverters exhibits similar to 323.75% enhancement compared to its JL RO at 10 nm node. (C) 2020 Elsevier GmbH. All rights reserved.
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页数：10
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