Analysis of Signal Integrity(SI) Robustness in Through-Silicon Interposer (TSI) Interconnects

被引:0
|
作者
Weerasekera, Roshan [1 ]
Cubillo, Joseph Romen [1 ]
Katti, Guruprasad [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the electrical characteristics of the tine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.
引用
收藏
页码:397 / 400
页数:4
相关论文
共 50 条
  • [31] A Calibrated Pathfinding Model for Signal Integrity Analysis on Interposer
    Kim, Jaemin
    Kim, Sunyoung
    Ryckaert, Julien
    Detalle, Mikael
    Van Hoovels, Nele
    Marchal, Pol
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [32] Electrical-thermal modeling of through-silicon via (TSV) arrays in interposer
    Xie, Jianyong
    Xie, Biancun
    Swaminathan, Madhavan
    INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2013, 26 (06) : 545 - 559
  • [33] Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)
    Kim, Seongguk
    Shin, Taein
    Park, Hyunwook
    Lho, Daehwan
    Son, Keeyoung
    Kim, Keunwoo
    Park, Joonsang
    Choi, Seonguk
    Kim, Jihun
    Kim, Haeyeon
    Kim, Joungho
    2021 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS (EDAPS), 2021,
  • [34] Enhancing Signal and Power Integrity Using Double Sided Silicon Interposer
    Sridharan, Vivek
    Swaminathan, Madhavan
    Bandyopadhyay, Tapobrata
    IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2011, 21 (11) : 598 - 600
  • [35] Interfacial electromagnetic-thermal characterization of a shielded pair through-silicon via a silicon interposer
    Liao, Chenguang
    Zhu, Zhangming
    Yang, Yintang
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2018, 33 (11)
  • [36] Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials
    Loh, Woon Leng
    Chui, King-Jien
    2020 IEEE 22ND ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2020, : 268 - 272
  • [37] The Cost Study of 300mm Through Silicon Interposer (TSI) with BEOL Interconnect
    Li, H. Y.
    Katti, Guruprasad
    Ding, L.
    Bhattacharya, Surya
    Lo, G. Q.
    PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 664 - 668
  • [38] Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface
    Kim, Hyunwoong
    Lee, Seonghi
    Park, Jongcheol
    Shin, Yujun
    Woo, Seongho
    Kim, Jongwook
    Cho, Jaeyong
    Ahn, Seungyoung
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2023, 13 (05): : 700 - 714
  • [39] Reliability study of through-silicon via (TSV) copper filled interconnects
    Kamto, A.
    Liu, Y.
    Schaper, L.
    Burkett, S. L.
    THIN SOLID FILMS, 2009, 518 (05) : 1614 - 1619
  • [40] Thermomechanical Reliability of Through-Silicon Vias in 3D Interconnects
    Lu, Kuan-Hsun
    Ryu, Suk-Kyu
    Im, Jay
    Huang, Rui
    Ho, Paul S.
    2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2011,