Design of a pseudo-log image transform IP in an HLS-based memory management framework

The pseudo-log image transform is essentially a logarithmic transformation that simulates the distribution of the eye's photoreceptors and finds application in many important areas of real time image and video processing such as motion detection and estimation in robots and foveated space variant cameras. It belongs to a family of non-linear image processing kernels in which references made to memory are non-linear functions of loop indices. Non-linear kernels need some form of memory management in order to achieve the required throughput, to minimize on-chip memory and to maximize possible data re-use. In this paper we present the design of a pseudo-log image processing hardware accelerator IP, integrated with different interpolation filtering techniques, using a memory management framework. The framework can automatically generate a memory hierarchy around the IP and a data transfer controller that facilitates data exchange with main memory. The memory hierarchy reduces on-chip memory requirements, optimizes throughput and increases data-reuse. The design of the IP is fully performed at the algorithmic level in C/C++. The algorithmic description is profiled within the framework to create a customized memory hierarchy, also described at the synthesizable algorithmic level. Finally, high level synthesis is used to perform hardware design space exploration and performance estimation. Experiments show that the generated memory hierarchy is able to feed the IP with a very high bandwidth even in presence of long external memory latencies.