Improved Device Characteristics in Charge-Trapping-Engineered Flash Memory Using High-κ Dielectrics

被引：2

作者：

Chin, Albert ^{[1
,2
]}

Lin, S. H. ^{[3
]}

Tsai, C. Y. ^{[1
]}

Yeh, F. S. ^{[3
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

[2] Nano Elect Consortium, Hsinchu, Taiwan

[3] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu, Taiwan

来源：

PHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 7 | 2009年 / 25卷 / 06期

关键词：

RETENTION;

D O I：

10.1149/1.3206644

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The much shallower trap energy in Si3N4 of [poly-Si]-SiO2-Si3N4-SiO2- Si (SONOS) charge-trapping flash (CTF) device than conventional poly-Si floating gate flash is the fundamental challenge for CTF device. We have pioneered the high-trapping layer CTF memory to increase the trapping energy, where the AlGaN has a large conduction band offset to barrier oxide layer close to conventional poly-Si floating gate. Further device performance improvement is achieved using the novel Charge-Trapping-Engineered Flash (CTEF) device with double barriers for carrier confinements and double shallow-/deep-trapping layers for charge storage. Excellent memory device integrities of large extrapolated 10-year retention of 3.8 V at 150 degrees C, 4 logic levels MLC operation, very fast 100 mu s write speed and good 100,000 cycling stress are measured at the same time. These excellent results may allow further down-scaling the flash memory for additional nodes.

引用

页码：447 / 455

页数：9

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