Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding

被引：14
|
作者：
Zhang, Peng [1 ,2 ]
Xie, Don [3 ]
Gao, Wen [4 ]
机构：
[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China
[2] Chinese Acad Sci, Grad Sch, Beijing 100049, Peoples R China
[3] Spreadtrum Commun Inc, Beijing 100084, Peoples R China
[4] Peking Univ, Digital Media Inst, Beijing 100871, Peoples R China
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2009年 / 17卷 / 03期
关键词：
CABAC; parallel architectures; real-time; video coding;
D O I：
10.1109/TVLSI.2008.2005286
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an efficient VLSI architecture for H.264/AVC content-adaptive binary arithmetic code (CABAC) decoding. We introduce several new techniques to maximize the parallelism of the decoding process, including variable-bin-rate strategy, multiple-bin arithmetic decoding, and efficient probability propagation scheme. The CABAC engine can ensure the real-time decoding for H.264/AVC main profile HD level 4.0. Synthesis results show that the multi-bin decoder can be operated tip to 45 MHz, and the total logic area is only 42 K gates when targeted at TSMC's 0.18-mu m process.
引用
收藏
页码：417 / 426
页数：10
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