共 30 条
[1]
Awasthi V., 2014, INT J ELECT ELECT CO, V2, P25
[2]
RATIONAL SAMPLING RATE CONVERSION STRUCTURES WITH MINIMUM DELAY REQUIREMENTS
[J].
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES,
1992, 139 (06)
:477-485
[4]
Chandrasekaran G., 2019, J. Europeen des Systemes Automatises, V52, P599, DOI [10.18280/jesa.520607, DOI 10.18280/JESA.520607.17G]
[6]
Test scheduling for system on chip using modified firefly and modified ABC algorithms
[J].
SN APPLIED SCIENCES,
2019, 1 (09)
[7]
Di J, 2003, IEEE COMP SOC ANN, P260, DOI 10.1109/ISVLSI.2003.1183490
[8]
Gustafsson O, 2006, CONF REC ASILOMAR C, P888
[9]
Hemantha GR, 2020, J SCI IND RES INDIA, V79, P135
[10]
Hsiao C., 1987, Proceedings: ICASSP 87. 1987 International Conference on Acoustics, Speech, and Signal Processing (Cat. No.87CH2396-0), P2173