Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters

被引:19
作者
Centurelli, Francesco [1 ]
Monsurro, Pietro [1 ]
Trifiletti, Alessandro [1 ]
机构
[1] Univ Roma La Sapienza, Dipartimento Ingn Informaz Elettron & Telecomunic, I-00184 Rome, Italy
关键词
Analog-to-digital (A/D) converter (ADC); digital background calibration; time interleaving;
D O I
10.1109/TCSII.2012.2235014
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conversion, even in the presence of wideband input signals and signals beyond the first Nyquist band. The proposed algorithm improves a previous work by the authors by allowing higher precision, particularly in the case of many interleaved channels and large mismatches. Accuracy improves by 3-8 bits with respect to the previous algorithm and up to 10 bits with respect to the uncalibrated case.
引用
收藏
页码:86 / 90
页数:5
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