Building manycore processor-to-DRAM networks with monolithic silicon photonics

被引：152

作者：

Batten, Christopher ^{[1
]}

Joshi, Ajay ^{[1
]}

Orcutt, Jason ^{[1
]}

Khilo, Anatoly ^{[1
]}

Moss, Benjamin ^{[1
]}

Holzwarth, Charles ^{[1
]}

Popovic, Milos ^{[1
]}

Li, Hanqing ^{[1
]}

Smith, Henry ^{[1
]}

Hoyt, Judy ^{[1
]}

Kartner, Franz ^{[1
]}

Ram, Rajeev ^{[1
]}

Stojanovic, Vladimir ^{[1
]}

Asanovic, Krste ^{[2
]}

机构：

[1] MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA

[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

16TH ANNUAL IEEE SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/HOTI.2008.11

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches. Our technology supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide. Simulation and experimental results reveal an order of magnitude better energy-efficiency than electrical links in the same technology generation. Exploiting key features of our photonics technology, we have developed a processor-memory network architecture for future manycore Systems based on an opto-electrical global crossbar. We illustrate the advantages of the proposed network architecture using analytical models and simulations with synthetic traffic patterns. For a power-constrained system with 256 cores connected to 16 DRAM modules using an opto-electrical crossbar, aggregate network throughput can be improved by approximate to 8-10x compared to an optimized purely electrical network.

引用

页码：21 / +

页数：2

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