Recovery of negative bias temperature instability induced degradation of p-MOSFETs with SiON gate dielectric

被引:3
|
作者
Kim, Y. D. [1 ]
Han, S. U. [1 ]
Kang, H. S. [1 ]
Kang, B. K. [1 ]
机构
[1] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 790784, Kyungpook, South Korea
关键词
MOSFET; reliability; silicon oxynitride; gate dielectric; negative bias temperature instability (NBTI);
D O I
10.1016/j.mee.2008.06.022
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper investigates the recovery property of p-MOSFETs with an ultra-thin SiON gate dielectric which are degraded by negative bias temperature instability (NBTI). The experimental results indicate that the recovery of the NBTI degradation occurs through an electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges was a fast process occurring just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the electron injection into the gate dielectric. Below the gate voltage for strong accumulation, the amount of recovery increased with an increase of the gate voltage. A further increase of gate voltage did not affect the amount of recovery. These experimental results indicate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons instead of a hydrogen passivation of the NBTI-induced defect sites. (C) 2008 Elsevier B.V. All rights reserved.
引用
收藏
页码:1932 / 1936
页数:5
相关论文
共 50 条
  • [41] Positive Bias Temperature Instability Degradation of InGaAs n-MOSFETs with Al2O3 Gate Dielectric
    Jiao, G. F.
    Cao, W.
    Xuan, Y.
    Huang, D. M.
    Ye, P. D.
    Li, M. F.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [42] A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide
    Suzuki, A
    Tabuchi, K
    Kimura, H
    Hasegawa, T
    Kadomura, S
    Kakamu, K
    Kudo, H
    Kawano, M
    Tsukune, A
    Yamada, M
    2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 216 - 217
  • [43] Negative-Bias Temperature Instability of GaN MOSFETs
    Guo, Alex
    del Alamo, Jesus A.
    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
  • [44] GATE-OXIDE THICKNESS DEPENDENCE OF HOT-CARRIER-INDUCED DEGRADATION IN BURIED P-MOSFETS
    HIROKI, A
    ODANAKA, S
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (05) : 1223 - 1228
  • [45] Asymmetric energy distribution of interface traps in n- and p-MOSFETs with HfO2 gate dielectric on ultrathin SiON buffer layer
    Han, JP
    Vogel, EM
    Gusev, EP
    D'Emic, C
    Richter, CA
    Heh, DW
    Suehle, JS
    IEEE ELECTRON DEVICE LETTERS, 2004, 25 (03) : 126 - 128
  • [46] A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs
    Tsujikawa, S
    Umeda, H
    Kawahara, T
    Kawasaki, Y
    Shiga, K
    Yamashita, T
    Hayashi, T
    Yugami, J
    Ohno, Y
    Yoneda, M
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 843 - 846
  • [47] Bipolar charge trapping induced anomalous negative bias-temperature instability in HfSiON gate dielectric pMOSFETs
    Tang, Chun-Jung
    Ma, Huan-Chi
    Wang, Tahui
    Chan, Chien-Tai
    Chang, Chih-Sheng
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2007, 7 (04) : 518 - 523
  • [48] A review of new characterization methodologies of gate dielectric breakdown and negative bias temperature instability
    Alam, M. A.
    IPFA 2006: PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2006, : 25 - 32
  • [49] Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode
    Ritenour, A
    Yu, S
    Lee, ML
    Lu, N
    Bai, W
    Pitera, A
    Fitzgerald, EA
    Kwong, DL
    Antoniadis, DA
    2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 433 - 436
  • [50] A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs
    Goel, N.
    Joshi, K.
    Mukhopadhyay, S.
    Nanaware, N.
    Mahapatra, S.
    MICROELECTRONICS RELIABILITY, 2014, 54 (03) : 491 - 519