An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors

Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.