A low-power variable resolution analog-to-digital converter

A method to reduce the power dissipation of analog-to-digital converters (ADCs) in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this paper, we present an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Our ADC is implemented in a 0.35 mum CMOS technology with a single-ended 3.3 V power supply. This ADC implementation has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits.