Design and Electrical Characterization of 2-T Thyristor RAM With Low Power Consumption

被引：12

作者：

Kim, Youngmin ^{[1
,2
]}

Kwon, Min-Woo ^{[3
]}

Ryoo, Kyung-Chang ^{[4
]}

Cho, Seongjae ^{[1
,2
]}

Park, Byung-Gook ^{[3
]}

机构：

[1] Gachon Univ, Grad Sch IT Convergence Engn, Seongnam 13120, South Korea

[2] Gachon Univ, Dept Elect Engn, Seongnam 13120, South Korea

[3] Seoul Natl Univ, Interuniv Semicond Res Ctr, Dept Elect & Informat Engn, Seoul 08826, South Korea

[4] Samsung Elect Co Ltd, Applicat Engn Team, Memory Div, Gyeonggi Do 18848, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2018年 / 39卷 / 03期

基金：

新加坡国家研究基金会;

关键词：

Thyristor; 2-T TRAM; TCAD; low power consumption; operation window; capacitorless DRAM; DRAM CELL;

D O I：

10.1109/LED.2018.2796139

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (T-write) and erase time (T-erase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10(5). Also, V-write and erase voltage (V-erase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

引用

页码：355 / 358

页数：4

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