A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and-104.7dBc THD in 30MHz BW

被引：3

作者：

Cenci, P. ^{[1
]}

Brekelmans, H. ^{[1
]}

Bajoria, S. ^{[1
]}

Ganzerli, M. ^{[1
]}

Burdiek, B. ^{[2
]}

Rutten, R. ^{[1
]}

Gao, Y. ^{[1
]}

Bolatkale, M. ^{[1
]}

Swinkels, P. ^{[3
]}

Breems, L. ^{[1
]}

机构：

[1] NXP Semiconductors, Eindhoven, Netherlands

[2] NXP Semiconductors, Hamburg, Germany

[3] NXP Semiconductors, Nijmegen, Netherlands

来源：

ESSCIRC 2022- IEEE 48TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2022年

关键词：

ADC; Delta Sigma; low flicker noise; high linearity; GHz chopper; wide bandwidth; 28nm; calibration; DESIGN; CONVERTERS;

D O I：

10.1109/ESSCIRC55480.2022.9911312

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 2GHz 2-bit continuous-time Delta Sigma ADC employing a 2GHz chopper to achieve low 1/f noise while maintaining high spectral purity over a 30MHz bandwidth. The proposed ADC achieves 12nV/(sqrt(Hz)) noise density at 153kHz, 78.5dB SNDR, -104.7dBc THD and better than 122dBFS SFDR (excluding HDx) in 30MHz BW. It is fabricated in a 28nm CMOS process consuming 61.4mW.

引用

页码：321 / 324

页数：4

共 7 条

[1] Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator [J].