Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance

被引：0
|
作者：
Hassoune, I. [1 ]
Yang, X. [1 ]
O'Connor, I. [1 ]
Navarro, D. [1 ]
机构：
[1] Univ Lyon, Lyon Inst Nanotechnol, UMR 5270, CNRS,Ecole Cent Lyon, Ecully, France
来源：
2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE | 2008年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a new efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance (NDR) device realized in a fully depleted (FD) silicon on insulator (SOI) double-gate (DG) MOSFET technology. Simulation results show significant (65%) power savings for asymmetric gate workfunction and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.
引用
收藏
页码：345 / 348
页数：4
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