Hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon TFTs

Hot-carrier injection is known to produce interface states and oxide trapped charge, which, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current flow. In this work, we analyze the hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon thin film transistors (TFTs) and a new model, which correlates the interface state generation with the hot carrier injection current, is proposed. The defect generation rate has been assumed to depend upon the product of hot electron and hole currents J h, and the resulting interface state distribution has been evaluated self-consistently with the current density and carrier concentration distributions. By successive iterations, a complete spatial and time evolution of the interface state distribution has been determined, and the electrical characteristics, calculated with these interface state distributions are in good agreement with the experimental data. The interface states are mainly generated at the back interface, thus explaining the relative insensitivity of the on-current measured at low-V-ds, to hot carrier-induced damage. On the other hand, the presence of interface states in this region has a major impact on the field and current distributions when the device is operated at high drain biases, as denoted by the drain current modifications observed in this regime. The interface state density expands, at both front and back interfaces, toward the drain contact and, as the damage progress, the interface state generation rate slows down, because the hot-carrier injection is progressively reduced by the increasing interface state density. Due to the accurate reproduction of the experimental data, it is possible to apply the present model to make predictions of the device behavior at very long times.