On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L-min approximate to 4.5(t(Si) + (epsilon(Si)/epsilon(I))t(I)), where t(Si) is the silicon thickness, and epsilon(I) and t(I) are the permittivity and thickness of the gate insulator. With t(Si) limited to >= 2 nm from quantum mechanical and threshold considerations, a scaling limit of L-min = 20 nm is projected for oxides, and L-min = 10 nm for high-kappa. dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.