Circuit techniques for ultra-low power subthreshold SRAMs

被引：16
|
作者：
Kim, Tae-Hyoung [1 ]
Liu, Jason [1 ]
Keane, John [1 ]
Kim, Chris H. [1 ]
机构：
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
来源：
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年
关键词：
D O I：
10.1109/ISCAS.2008.4541982
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Subthreshold operation has become an important area in applications where minimal power consumption and energy efficiency are the critical constraints. In particular, ultra-low power SRAM designs are critical for implementing such applications due to the large portion of the systems that they account for. However, sub-threshold SRAMs have many design issues such as cell stability, readability, and writability. In this paper, we give an overview of sub-threshold SRAM design issues and discuss several circuit techniques. We will focus on SRAM cell stability during read and write operation, improved writability, and read port circuits for the design of an ultra-low power sub-threshold SRAMs.
引用
收藏
页码：2574 / 2577
页数：4
相关论文
共 50 条
  • [11] Analysis of subthreshold FinFET circuits for ultra-low power design
    Wu, Xiaoxia
    Wang, Feng
    Xie, Yuan
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2006, : 91 - +
  • [12] Subthreshold pass transistor logic for ultra-low power operation
    Moalemi, Vahid
    Afzali-Kusha, Ali
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2007, : 490 - +
  • [13] A new ultra-low power wide tunable capacitance multiplier circuit in subthreshold region for biomedical applications
    Jeshvaghani, Mohammad Aghaei
    Dolatshahi, Mehdi
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 177
  • [14] Design of Advanced Subthreshold SRAM Array for Ultra-Low Power Technology
    Kim, Taehoon
    Kim, Hyunmyoung
    Chung, Yeonbae
    2018 5TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC ENGINEERING (ICEEE), 2018, : 329 - 333
  • [15] Double gate MOSFET subthreshold logic for ultra-low power applications
    Kim, JJ
    Roy, K
    2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 97 - 98
  • [16] Analysis on the Ultra-low Power Integrated Circuit Technology
    Lin, Meidong
    Wen, Zhiping
    Chen, Lei
    PROCEEDINGS OF THE 4TH INTERNATIONAL CONFERENCE ON MECHATRONICS, MATERIALS, CHEMISTRY AND COMPUTER ENGINEERING 2015 (ICMMCCE 2015), 2015, 39 : 2642 - 2644
  • [17] CMOS technology for ultra-low power circuit applications
    Salomonson, CD
    Henley, WB
    Whittaker, DR
    Maimon, J
    IEEE SOUTHEASTCON '97 - ENGINEERING THE NEW CENTURY, PROCEEDINGS, 1996, : 233 - 235
  • [18] Standby Power Reduction Techniques for Ultra-Low Power Processors
    Lee, Yoonmyung
    Seok, Mingoo
    Hanson, Scott
    Blaauw, David
    Sylvester, Dennis
    ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 186 - 189
  • [19] FDSOI Process Technology for Subthreshold-Operation Ultra-Low Power Electronics
    Vitale, S. A.
    Wyatt, P. W.
    Checka, N.
    Kedzierski, J.
    Keast, C. L.
    ADVANCED SEMICONDUCTOR-ON-INSULATOR TECHNOLOGY AND RELATED PHYSICS 15, 2011, 35 (05): : 179 - 188
  • [20] An Ultra-Low Power CMOS Subthreshold Voltage Reference with Temperature Coefficient Compensation
    Huang, Yuxuan
    Wu, Ruihuang
    Xiong, Bingjun
    Li, Zhipeng
    Liu, Jia
    Zou, Yun
    Liu, Jingjing
    Sun, Xinghua
    PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS, AND SYSTEMS, ICCCAS 2023, 2024, 1193 : 187 - 197
12345