Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems

被引:22
作者
He, Ku [1 ]
Gerstlauer, Andreas [2 ]
Orshansky, Michael [2 ]
机构
[1] Cirrus Log Inc, Austin, TX 78701 USA
[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
基金
美国国家科学基金会;
关键词
Error tolerant computing; low energy design; LOW-POWER;
D O I
10.1109/TCSVT.2013.2243658
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An intrinsic notion of quality floors present in typical digital signal processing circuits can be used to strategically accept some runtime errors in exchange for a reduction in energy consumption. Conventional very large scale integration design strategies do not exploit this degree of error tolerance and aim to guarantee timing correctness, thereby sacrificing energy efficiency. In this paper, we propose techniques for timing error acceptance to improve the quality-energy tradeoff in image and video processing systems under scaled V-DD. The basic philosophy is to prevent signal quality from severe degradation, on average, by using data statistics. The introduced innovations include techniques for carefully controlling possible errors and exploiting the specifics of error patterns for low-cost postprocessing to minimize quality degradation. We demonstrate the effectiveness of the proposed techniques on a 2-D inverse discrete cosine transform (IDCT) and a 2-D DCT design. The designs were synthesized using a 45-nm standard cell library, with energy and delay evaluated using NanoSim and VCS. Experiments show that direct applications of controlled error-acceptance techniques allow up to 59% and 71% energy savings by permitting fewer than 1-dB peak signal-to-noise ratio (PSNR) decrease for the 2-D IDCT and DCT designs, respectively. The resulting PSNR remains above 30 dB, which is a commonly accepted value for lossy image and video compression. Achieving such energy savings by direct V-DD scaling without the proposed transformations results in a 12-dB PSNR loss. The area overhead for the needed control logic is about 4.8% of the original design. To further minimize quality degradation caused by accepted errors in the IDCT, we introduce postfiltering on the output image. The significant improvement of the perceived image quality allows further voltage scaling leading to overall energy savings of 70% for the 2-D IDCT, while costing an additional 1.1% in area.
引用
收藏
页码:961 / 974
页数:14
相关论文
共 24 条
[1]  
Albicocco P., 2012, P 46 AS C SIGN SYST, P5
[2]  
Anastasia D, 2009, IEEE WRK SIG PRO SYS, P249, DOI 10.1109/SIPS.2009.5336260
[3]   DOES MEDIAN FILTERING TRULY PRESERVE EDGES BETTER THAN LINEAR FILTERING? [J].
Arias-Castro, Ery ;
Donoho, David L. .
ANNALS OF STATISTICS, 2009, 37 (03) :1172-1206
[4]  
Banerjee N., 2007, 2007 Design, Automation Test in Europe Conference Exhibition, P1
[5]   MINIMIZING POWER-CONSUMPTION IN DIGITAL CMOS CIRCUITS [J].
CHANDRAKASAN, AP ;
BRODERSEN, RW .
PROCEEDINGS OF THE IEEE, 1995, 83 (04) :498-523
[6]   CRISTA: a new paradigm for low-power, variation,-tolerant, and adaptive circuit synthesis using critical path isolation [J].
Ghosh, Swaroop ;
Bhunia, Swarup ;
Roy, Kaushik .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (11) :1947-1956
[7]  
He K., 2011, P DES AUT TEST EUR C, P492
[8]   Soft digital signal processing [J].
Hegde, R ;
Shanbhag, NR .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (06) :813-823
[9]  
Karakonstantis G, 2009, IEEE WRK SIG PRO SYS, P133, DOI 10.1109/SIPS.2009.5336238
[10]   Low-Power Multimedia System Design by Aggressive Voltage Scaling [J].
Kurdahi, Fadi J. ;
Eltawil, Ahmed ;
Yi, Kang ;
Cheng, Stanley ;
Khajeh, Amin .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (05) :852-856