Towards Structured ASICs using Polarity-Tunable Si Nanowire Transistors

被引：0

作者：

Gaillardon, Pierre-Emmanuel ^{[1
]}

De Marchi, Michele ^{[1
]}

Amaru, Luca ^{[1
]}

Bobba, Shashikanth ^{[1
]}

Sacchetto, Davide ^{[1
]}

Leblebici, Yusuf

De Micheli, Giovanni ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, Integrated Syst Lab LSI, CH-1015 Lausanne, Switzerland

来源：

2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2013年

关键词：

Nanowire transistors; controllable polarity; regular fabrics; XOR logic synthesis;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications.

引用

页数：4