Trap layer engineered gate-all-around vertically stacked twin Si-nanowire nonvolatile memory

被引:18
作者
Fu, J. [1 ]
Buddharaju, K. D. [1 ]
Teo, S. H. G. [1 ]
Zhu, Chunxiang [1 ]
Yu, M. B. [1 ]
Singh, N. [1 ]
Lo, G. Q. [1 ]
Balasubramanian, N. [1 ]
Kwong, D. L. [1 ]
机构
[1] Inst Microelect, Singapore 117685, Singapore
来源
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年
关键词
D O I
10.1109/IEDM.2007.4418868
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V Delta V-th shift for 1 mu s and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.
引用
收藏
页码:79 / 82
页数:4
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