Low leakage 3xVDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process

被引：4

作者：

Yang ZhaoNian ^{[1
]}

Liu HongXia ^{[1
]}

Wang ShuLong ^{[1
]}

机构：

[1] Xidian Univ, Key Lab Wide Bandgap Semicond Mat & Devices, Sch Microelect, Minist Educ13at, Xian 710071, Peoples R China

来源：

SCIENCE CHINA-TECHNOLOGICAL SCIENCES | 2013年 / 56卷 / 08期

基金：

中国国家自然科学基金;

关键词：

detection circuit; electrostatic discharge (ESD); leakage current; over-stress voltage; stacked-transistors; CLAMP CIRCUIT; PROTECTION; DESIGN;

D O I：

10.1007/s11431-013-5278-2

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A new low leakage 3xVDD-tolerant electrostatic discharge (ESD) detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process. Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current. No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well. The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier (STSCR) under the ESD stress. Under normal operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 88 nA under 3xVDD bias at 25A degrees C. The simulation result shows the circuit can be successfully used for 3xVDD-tolerant I/O buffer.

引用

页码：2046 / 2051

页数：6