Fast, minimal decoding complexity, system level, binary systematic (41,32) single-error-correcting codes for on-chip DRAM applications

被引：4

作者：

Kazéminéjad, A ^{[1
]}

Belhaire, E ^{[1
]}

机构：

[1] Univ Paris 11, Inst Elect Fondamentale, F-91405 Orsay, France

来源：

2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/DFTVS.2001.966783

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Fast, minimal decoding complexity, System level, binary systematic (41, 32) single-error-correcting codes for On-chip DRAM applications are presented. These (41, 32) codes allow fast single error correcting with three parity bit penalty and can be used in combinational circuits with minimal (ultimate) decoding complexity.

引用

页码：308 / 313

页数：6