Noise characteristics and modeling of silicon-on-insulator insulated-gate pn-junction devices

This article describes the noise characteristics of various silicon-on-insulator insulated-gate pn-junction devices with anode-offset regions. The static characteristics of these devices are modeled for the noise analysis; the model is composed of a series of a metal-oxide-semiconductor field-effect transistors and the pn junction. It is shown experimentally that the noise power of the devices is proportional to I-n (n>0), where I is the anode current. Since the noise characteristics are not explained by the conventional theory, a phenomenological model is proposed. It is shown that the proposed basic model, which is compatible with the conventional Hooge model, can explain the experimental results. The influence of anode-offset length is also discussed and modeled. (C) 2002 American Institute of Physics.