An On-Chip Circuit for Timing Measurement of SRAM IP

被引：0

作者：

Long, Xianjie ^{[1
]}

Wang, Qin ^{[1
]}

Jiang, Jianfei ^{[1
]}

Guan, Nin ^{[2
]}

机构：

[1] Shanghai Jiao Tong Univ, Sch Microelect, Shanghai 200240, Peoples R China

[2] Shanghai Inst Aerosp Elect Commun Equipment, Shanghai 201108, Peoples R China

来源：

2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2017年

关键词：

Timing measurement; SRAM IP; DTC; SoC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The timing of silicon IPs should be measured before they are integrated into chips. Embedded solutions are needed for timing measurement of silicon IPs. This paper introduces a circuit design for timing measurement of SRAM IP. A new circuit is designed for the measurement of setup time, hold time and access time. This circuit is fabricated in SMIC 130nm CMOS technology. Testing results show that the proposed circuit can achieve an accuracy of 9.0ps with a good linearity. The timing measurement circuit has configurable capability and could be applied to the timing measurement of SRAM IPs.

引用

页码：569 / 572

页数：4

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