Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters

被引:21
|
作者
Yu, Bo [1 ]
Mak, Terrence [2 ,3 ]
Li, Xiangyu [1 ]
Xia, Fei [2 ]
Yakovlev, Alexandre [2 ]
Sun, Yihe [1 ]
Poon, Chi-Sang [4 ]
机构
[1] Tsinghua Univ, Inst Microelect, Tsinghua Natl Lab Informat Sci & Technol, Beijing 100084, Peoples R China
[2] Newcastle Univ, Sch Elect Elect & Comp Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
[3] Newcastle Univ, Inst Neurosci, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
[4] MIT, Harvard Mit Div Hlth Sci & Technol, Cambridge, MA 02139 USA
基金
北京市自然科学基金; 英国工程与自然科学研究理事会; 中国国家自然科学基金; 美国国家卫生研究院;
关键词
Brain-machine interface (BMI); field-programmable gate array (FPGAs); hardware architecture design; Hebbian learning; spike sorting; INTERFACE; DESIGN; SYSTEM;
D O I
10.1109/JETCAS.2012.2183430
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Real-time multichannel neuronal signal recording has spawned broad applications in neuro-prostheses and neuro-rehabilitation. Detecting and discriminating neuronal spikes from multiple spike trains in real-time require significant computational efforts and present major challenges for hardware design in terms of hardware area and power consumption. This paper presents a Hebbian eigenfilter spike sorting algorithm, in which principal components analysis (PCA) is conducted through Hebbian learning. The eigenfilter eliminates the need of computationally expensive covariance analysis and eigenvalue decomposition in traditional PCA algorithms and, most importantly, is amenable to low cost hardware implementation. Scalable and efficient hardware architectures for real-time multichannel spike sorting are also presented. In addition, folding techniques for hardware sharing are proposed for better utilization of computing resources among multiple channels. The throughput, accuracy and power consumption of our Hebbian eigenfilter are thoroughly evaluated through synthetic and real spike trains. The proposed Hebbian eigenfilter technique enables real-time multichannel spike sorting, and leads the way towards the next generation of motor and cognitive neuro-prosthetic devices.
引用
收藏
页码:502 / 515
页数:14
相关论文
共 50 条
  • [31] Advanced, Real-Time Programmable FPGA-Based Digital Filtering Unit for IR Detection Modules
    Achtenberg, Krzysztof
    Szplet, Ryszard
    Bielecki, Zbigniew
    ELECTRONICS, 2024, 13 (22)
  • [32] FPGA-based implementation of a real time photovoltaic module simulator
    Mekki, H.
    Mellit, A.
    Kalogirou, S. A.
    Messai, A.
    Furlan, G.
    PROGRESS IN PHOTOVOLTAICS, 2010, 18 (02): : 115 - 127
  • [33] Implementation of FPGA-based real time novel chaotic oscillator
    Koyuncu, Ismail
    Ozcerit, Ahmet Turan
    Pehlivan, Ihsan
    NONLINEAR DYNAMICS, 2014, 77 (1-2) : 49 - 59
  • [34] Teaching Real-Time Video Processing Theory by Using an FPGA-Based Educational System and the "Learning-by-Doing" Method
    Guzman-Ramirez, Enrique
    Garcia, Ivan
    Gonzalez, Carlos
    Mendoza-Manzano, Manuel
    COMPUTER APPLICATIONS IN ENGINEERING EDUCATION, 2017, 25 (03) : 376 - 391
  • [35] A Neuromorphic Brain Interface Based on RRAM Crossbar Arrays for High Throughput Real-Time Spike Sorting
    Shi, Yuhan
    Ananthakrishnan, Akshay
    Oh, Sangheon
    Liu, Xin
    Hota, Gopabandhu
    Cauwenberghs, Gert
    Kuzum, Duygu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (04) : 2137 - 2144
  • [36] Multichannel Synchronous Real-Time Transcranial Magnetic Stimulation Magnetic Field Detection System Based on FPGA
    Liu, Jinzhen
    Nie, Chao
    Xiong, Hui
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2022, 71
  • [37] An FPGA-Based Hardware Architecture of Gaussian-Adaptive Bilateral Filter for Real-Time Image Denoising
    Xie, Ailin
    Zhang, Ao
    Mei, Guohui
    IEEE ACCESS, 2024, 12 : 115277 - 115285
  • [38] Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters
    Lucia, Oscar
    Urriza, Isidro
    Barragan, Luis. A.
    Navarro, Denis
    Jimenez, Oscar
    Burdio, Jose M.
    IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2011, 47 (02) : 853 - 860
  • [39] FPGA-based real time controller for high order correction in EDIFISE
    Rodriguez-Ramos, L. F.
    Chulani, H.
    Martin, Y.
    Dorta, T.
    Alonso, A.
    Fuensalida, J. J.
    ADAPTIVE OPTICS SYSTEMS III, 2012, 8447
  • [40] Compact standalone platform for neural recording with real-time spike sorting and data logging
    Luan, Song
    Williams, Ian
    Maslik, Michal
    Liu, Yan
    De Carvalho, Felipe
    Jackson, Andrew
    Quiroga, Rodrigo Quian
    Constandinou, Timothy G.
    JOURNAL OF NEURAL ENGINEERING, 2018, 15 (04)