OpenCL for HPC with FPGAs: Case Study in Molecular Electrostatics

被引:0
|
作者
Yang, Chen [1 ]
Sheng, Jiayi [1 ]
Patel, Rushi [1 ]
Sanaullah, Ahmed [1 ]
Sachdeva, Vipin [2 ]
Herbordt, Martin C. [1 ]
机构
[1] Boston Univ, Dept Elect & Comp Engn, Boston, MA 02215 USA
[2] Silicon Therapeut, Boston, MA USA
基金
美国国家科学基金会;
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
FPGAs have emerged as a cost-effective accelerator alternative in clouds and clusters. Programmability remains a challenge, however, with OpenCL being generally recognized as a likely part of the solution. In this work we seek to advance the use of OpenCL for HPC on FPGAs in two ways. The first is by examining a core HPC application, Molecular Dynamics. The second is by examining a fundamental design pattern that we believe has not yet been described for OpenCL: passing data from a set of producer datapaths to a set of consumer datapaths, in particular, where the producers generate data non-uniformly. We evaluate several designs: single level versions in Verilog and in OpenCL, a two-level Verilog version with optimized arbiter, and several two-level OpenCL versions with different arbitration and hand-shaking mechanisms, including one with an embedded Verilog module. For the Verilog designs, we find that FPGAs retain their high-efficiency with a factor of 50x to 80x performance benefit over a single core. We also find that OpenCL may be competitive with HDLs for the straightline versions of the code, but that for designs with more complex arbitration and hand-shaking, relative performance is substantially diminished.
引用
收藏
页数:8
相关论文
共 50 条
  • [11] OpenCL Memory Infrastructure for FPGAs
    Chin, S. Alexander
    Chow, Paul
    FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2012, : 269 - 270
  • [12] SYSTEM DESIGN EXPLORATION WITH OPENCL FOR FPGAS
    Denisenko, Dmitry
    Popryaga, Mykhailo
    ELECTRONICS WORLD, 2015, 121 (1952): : 26 - 29
  • [13] Tuning Stencil Codes in OpenCL for FPGAs
    Jia, Qi
    Zhou, Huiyang
    PROCEEDINGS OF THE 34TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2016, : 249 - 256
  • [14] Optimized implementation of OpenCL kernels on FPGAs
    Shata, Kholoud
    Elteir, Marwa K.
    EL-Zoghabi, Adel A.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2019, 97 : 491 - 505
  • [15] Resource Elastic Virtualization for FPGAs using OpenCL
    Vaishnav, Anuj
    Khoa Dang Pham
    Koch, Dirk
    Garside, James
    2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 111 - 118
  • [16] FIexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs
    Liang, Yun
    Wang, Shuo
    Zhang, Wei
    IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (12) : 1750 - 1764
  • [17] Melia: A MapReduce Framework on OpenCL-Based FPGAs
    Wang, Zeke
    Zhang, Shuhao
    He, Bingsheng
    Zhang, Wei
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2016, 27 (12) : 3547 - 3560
  • [18] Exploring Pipe Implementations using an OpenCL Framework for FPGAs
    Mirian, Vincent
    Chow, Paul
    2015 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (FPT), 2015, : 112 - 119
  • [19] Developing Optimized Libraries for Scalable OpenCL Acceleration on FPGAs
    Vallina, Fernando Martinez
    Varma, Devadas
    Singh, Vinay
    International Workshop on OpenCL 2015, 2015,
  • [20] A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs
    Wang, Zeke
    He, Bingsheng
    Zhang, Wei
    Jiang, Shunning
    PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA-22), 2016, : 114 - 125