An Efficient FPGA-Based Architecture for Convolutional Neural Networks

被引：0
|
作者：
Hwang, Wen-Jyi [1 ]
Jhang, Yun-Jie [1 ]
Tai, Tsung-Ming [1 ]
机构：
[1] Natl Taiwan Normal Univ, Dept Comp Sci & Informat Engn, Taipei, Taiwan
来源：
2017 40TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP) | 2017年
关键词：
artificial vision systems; convolutional neural networks; field programmable gate array; hardware architecture; pipeline operations; COPROCESSOR;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.
引用
收藏
页码：582 / 588
页数：7
相关论文
共 50 条
  • [21] FPGA-based architecture for computing testors
    Rojas, Alejandro
    Cumplido, Rene
    Carrasco-Ochoa, J. Ariel
    Feregrino, Claudia
    Martinez-Trinidad, J. Francisco
    INTELLIGENT DATA ENGINEERING AND AUTOMATED LEARNING - IDEAL 2007, 2007, 4881 : 188 - 197
  • [22] Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators
    Ali, Nermine
    Philippe, Jean-Marc
    Tain, Benoit
    Coussy, Philippe
    2021 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2021), 2021, : 123 - 128
  • [23] FPGA-based reflection image removal using cognitive neural networks
    Saptalakar, Bairu K.
    Latte, Mrityunjaya, V
    APPLIED NANOSCIENCE, 2022, 13 (3) : 2539 - 2553
  • [24] A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA
    Bacis, Marco
    Natale, Giuseppe
    Del Sozzo, Emanuele
    Santambrogio, Marco Domenico
    2017 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2017, : 90 - 97
  • [25] Assessing the Reliability of FPGA-Based Quantized Neural Networks Under Neutron Irradiation
    Souvatzoglou, Ioanna
    Agiakatsikas, Dimitris
    Vlagkoulis, Vasileios
    Sari, Aitzan
    Psarakis, Mihalis
    Kastriotou, Maria
    Cazzaniga, Carlo
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2024, 71 (12) : 2565 - 2577
  • [26] Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network
    Shah, Nimish
    Chaudhari, Paragkumar
    Varghese, Kuruvilla
    IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 2018, 29 (12) : 5922 - 5934
  • [27] Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
    Wang, Maolin
    Lee, Kelvin C. M.
    Chung, Bob M. F.
    Bogaraju, Sharatchandra Varma
    Ng, Ho-Cheung
    Wong, Justin S. J.
    Shum, Ho Cheung
    Tsia, Kevin K.
    So, Hayden Kwok-Hay
    IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 2022, 33 (07) : 2853 - 2866
  • [28] COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks based on Systolic Array
    Yin, Chen
    Chen, Qiang
    Tian, Miren
    Ji, Mohan
    Zou, Chenglong
    Wang, Yin'an
    Wang, Bo
    2017 IEEE 23RD INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2017, : 180 - 189
  • [29] An FPGA-Based Autofocusing Hardware Architecture for Digital Holography
    Chen, Huan-Yuan
    Hwang, Wen-Jyi
    Cheng, Chau-Jern
    Lai, Xin-Ji
    IEEE TRANSACTIONS ON COMPUTATIONAL IMAGING, 2019, 5 (02) : 287 - 300
  • [30] Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks
    Dong, Yong
    Hu, Wei
    Wang, Yonghao
    Jiao, Qiang
    Chen, Shuang
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2020, PT II, 2020, 12453 : 97 - 110
12345