Architectural trends in current-steering digital-to-analog converters

被引：10

作者：

Balasubramanian, S. ^{[1
]}

Khalil, W. ^{[1
]}

机构：

[1] Electrosci Lab, Dept Elect & Comp Engn, Columbus, OH 43212 USA

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2013年 / 77卷 / 01期

关键词：

Digital-to-analog converters (DACs); Interleaving; Reconstruction; GHz; Trends; Architectures; DACS DYNAMIC SFDR; DELTA-SIGMA; CMOS DAC; RF DAC; IMPROVEMENT; DBC;

D O I：

10.1007/s10470-013-0082-2

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent interests from the research community in building digitized transmitters have led to numerous architectural and circuit-level innovations and developments towards the design of digital-to-analog converters (DACs) in the GHz space. However, several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the accuracy, linearity and achievable speed. This paper aims to highlight some of the fundamental challenges in DACs and provide the reader with an insight into some of the emerging innovations at the systemic and circuit levels that address these challenges and aid in the transition of high-resolution DACs into the GHz regime.

引用

页码：55 / 67

页数：13

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