Adaptive Page Allocation of DRAM/PCRAM Hybrid Memory Architecture

被引：0

作者：

Cheng, Wei-Kai ^{[1
]}

Cheng, Pi-Chieh ^{[1
]}

Li, Xin-Lun ^{[1
]}

机构：

[1] Chung Yuan Christian Univ, Dept Informat & Comp Engn, Taoyuan 32023, Taiwan

来源：

2016 5TH INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE) | 2016年

关键词：

page allocation; DRAM; PCRAM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.

引用

页数：2

共 44 条

[31] PRO: A periodical reset optimized page migration scheme for hybrid memory system [J].

Niu, Na ;

Fu, Fangfa ;

Yang, Bing ;

Yuan, Jiacai ;

Lai, Fengchang ;

Zhao, Chengxin ;

Wang, Jinxiang .

JOURNAL OF SYSTEMS ARCHITECTURE, 2020, 111

[32] A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers [J].

Singh, Gian ;

Vrudhula, Sarma .

PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, 2024, :57-62

[33] A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation [J].

Chen, Xianmin ;

Jha, Niraj K. .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (05) :1649-1662

[34] A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-Core/Many-Core Architecture [J].

Chen, Licheng ;

Huang, Yongbing ;

Bao, Yungang ;

Tan, Guangming ;

Cui, Zehan ;

Chen, Mingyu .

2013 12TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS (TRUSTCOM 2013), 2013, :1206-1215

[35] High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture [J].

Lee, Hyunsoo ;

Lee, Hyundong ;

Shin, Minseung ;

Shin, Gyuri ;

Jeon, Sumin ;

Song, Taigon .

2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC, 2023, :101-102

[36] Low Overhead Software Wear Leveling for Hybrid PCM plus DRAM Main Memory on Embedded Systems [J].

Hu, Jingtong ;

Xie, Mimi ;

Pan, Chen ;

Xue, Chun Jason ;

Zhuge, Qingfeng ;

Sha, Edwin H-M. .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (04) :654-663

[37] SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories [J].

Aswathy, N. S. ;

Bhavanasi, SreeSiddhesh ;

Sarkar, Arnab ;

Kapoor, Hemangee K. .

PROCEEDINGS OF THE 32ND GREAT LAKES SYMPOSIUM ON VLSI 2022, GLSVLSI 2022, 2022, :217-222

[38] Towards DRAM-Flash hybrid: Dual-speed low-voltage ferroelectric and charge memory [J].

Rajwade, Shantanu R. ;

Auluck, Kshitij ;

Jayant, Krishna ;

Kan, Edwin C. ;

Naoi, Taro A. ;

van Dover, R. B. .

2013 5TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2013, :166-169

[39] AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems [J].

Peng, Zhouxuan ;

Feng, Dan ;

Chen, Jianxi ;

Hu, Jing ;

Liu, Yachun ;

Hu, Jinlei ;

Zhang, Jintong ;

Wan, Tianyu ;

Chen, Zuoning .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 44 (03) :923-936

[40] SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading [J].

Yu, Wing-kei S. ;

Huang, Ruirui ;

Xu, Sarah Q. ;

Wang, Sung-En ;

Kan, Edwin ;

Suh, G. Edward .

ISCA 2011: PROCEEDINGS OF THE 38TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2011, :247-258

← 1 2 3 4 5 →