Adaptive Page Allocation of DRAM/PCRAM Hybrid Memory Architecture

被引：0

作者：

Cheng, Wei-Kai ^{[1
]}

Cheng, Pi-Chieh ^{[1
]}

Li, Xin-Lun ^{[1
]}

机构：

[1] Chung Yuan Christian Univ, Dept Informat & Comp Engn, Taoyuan 32023, Taiwan

来源：

2016 5TH INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE) | 2016年

关键词：

page allocation; DRAM; PCRAM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.

引用

页数：2

共 44 条

[21] EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory [J].

Shin, Ho Hyun ;

Park, Young Min ;

Choi, Duheon ;

Kim, Byoung Jin ;

Cho, Dae-Hyung ;

Chung, Eui-Young .

IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (01) :32-44

[22] CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement [J].

Lin, Chuxiong ;

He, Weifeng ;

Sun, Yanan ;

Mao, Zhigang ;

Seok, Mingoo .

2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2021, :1093-1098

[23] A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs [J].

Sudarshan, Chirag ;

Soliman, Taha ;

De la Parra, Cecilia ;

Weis, Christian ;

Ecco, Leonardo ;

Jung, Matthias ;

Wehn, Norbert ;

Guntoro, Andre .

2021 26TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2021, :35-42

[24] Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory [J].

Paul, Onkar ;

Mueller, Frank ;

Ionkov, Latchesar ;

Lee, Jason ;

Lang, Michael .

2020 IEEE 28TH INTERNATIONAL SYMPOSIUM ON MODELING, ANALYSIS, AND SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS (MASCOTS 2020), 2020, :111-118

[25] PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems [J].

Niu, Na ;

Fu, Fangfa ;

Yang, Bing ;

Wang, Qiang ;

Li, Xinpeng ;

Lai, Fengchang ;

Wang, Jinxiang .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (10) :1685-1692

[26] New three-dimensional memory array architecture for future ultrahigh-density DRAM [J].

Endoh, T ;

Shinmei, K ;

Sakuraba, H ;

Masuoka, F .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (04) :476-483

[27] Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning [J].

He, Mingxuan ;

Song, Choungki ;

Kim, Ilkon ;

Jeong, Chunseok ;

Kim, Seho ;

Park, Il ;

Thottethodi, Mithuna ;

Vijaykumar, T. N. .

2020 53RD ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO 2020), 2020, :372-385

[28] Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM [J].

Jing, Weiliang ;

Yang, Kai ;

Lin, Yinyin ;

Lee, Beomseop ;

Yoon, Sangkyu ;

Ye, Yong ;

Du, Yuan ;

Chen, Bomy .

IEEE TRANSACTIONS ON COMPUTERS, 2017, 66 (05) :912-918

[29] Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB [J].

Han, Miseon ;

Na, Yeoul ;

Jung, Dongha ;

Lee, Hokyoon ;

Wook Kim, Seon ;

Han, Youngsun .

IEICE TRANSACTIONS ON ELECTRONICS, 2018, E101C (03) :170-182

[30] RHPM: Using Relative Hotness to Guide Page Migration for Hybrid Memory Systems [J].

Peng, Zhouxuan ;

Feng, Dan ;

Chen, Jianxi ;

Hu, Jing ;

Huang, Chuang .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (08) :2514-2526

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