Low voltage swing gates for low power consumption

被引：0
|
作者：
Rjoub, A [1 ]
Koufopavlou, O [1 ]
机构：
[1] Univ Patras, Dept Elect & Comp Engn, VLSI Design Lab, GR-26500 Patras, Greece
来源：
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A low swing voltage design technique is proposed. The new design could be used successfully in order to decrease the power dissipation in Complementary Pass-Transistor Logic (CPL) as in Cascade Voltage Switch Logic (CVSL) logic gates. The achieved gate output voltage-level swing reduction, results in a significant reduction of their power consumption. Using the proposed technique, for supply voltage 3.3V and 0.5 mu m process technology, 35% (for the CPL) and 20% (for the CVSL) power consumption savings is achieved. Improvements in power-delay product are also obtained. In the new gates no special circuit design receiver is required in order to pull-up the low swing signal.
引用
收藏
页码：234 / 237
页数：4
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