Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs

被引：65

作者：

Poli, Stefano ^{[1
,2
]}

Pala, Marco G. ^{[3
]}

Poiroux, Thierry ^{[2
]}

Deleonibus, Simon ^{[2
]}

Baccarani, Giorgio ^{[1
]}

机构：

[1] Univ Bologna, Adv Res Ctr Elect Syst, I-40122 Bologna, Italy

[2] CEA LETI MINATEC, F-38054 Grenoble, France

[3] UMR CNRS INPG UJF 5130, MINATEC, IMEP LAHC, F-38016 Grenoble, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 11期

关键词：

Effective mobility; nonequilibrium Green's functions (NEGFs); quasi-ballistic transport; silicon nanowire (Si-NW); surface roughness (SR);

D O I：

10.1109/TED.2008.2005164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Lateral size effects on surface-roughness-limited mobility in silicon-nanowire FETs are analyzed by means of a full-quantum 3-D self-consistent simulation. A statistical analysis Is carried out by considering different realizations of the potential roughness at the Si-SiO2 interfaces. Nanowires with lateral section varying from 3 x 3 to 7 x 7 nm(2) are considered. Effective mobility is computed by evaluating the electron density in a reduced channel region to eliminate parasitic effects from contacts. It is found that transport in wires with the smallest section is dominated by scattering due to potential fluctuations, resulting in a larger standard deviation of the effective mobility, whereas it is dominated by transverse-mode coupling in wires with larger section, resulting in a stronger influence of surface roughness at high gate voltages.

引用

页码：2968 / 2976

页数：9

共 28 条

[1] [Anonymous], 2006, Electron Devices Meeting
[2] 4-TERMINAL PHASE-COHERENT CONDUCTANCE
BUTTIKER, M
[J]. PHYSICAL REVIEW LETTERS, 1986, 57 (14) : 1761 - 1764
[3] Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors
Chaisantikulwat, W.
Mouis, M.
Ghibaudo, G.
Gallon, C.
Fenouillet-Beranger, C.
Maude, D. K.
Skotnicki, T.
CristoloveanU, S.
[J]. SOLID-STATE ELECTRONICS, 2006, 50 (04) : 637 - 643
[4] CROS A, 2006, IEDM, P663
[5] Functional nanoscale electronic devices assembled using silicon nanowire building blocks
Cui, Y
Lieber, CM
[J]. SCIENCE, 2001, 291 (5505) : 851 - 853
[6] SURFACE-ROUGHNESS AT THE SI(100)-SIO2 INTERFACE
GOODNICK, SM
FERRY, DK
WILMSEN, CW
LILIENTAL, Z
FATHY, D
KRIVANEK, OL
[J]. PHYSICAL REVIEW B, 1985, 32 (12): : 8171 - 8186
[7] Monte Carlo study of apparent mobility reduction in nano-MOSFETs
Huet, K.
Saint-Martm, J.
Bournel, A.
Galdin-Retailleau, S.
Dollfus, P.
Ghibaudo, G.
Mouis, M.
[J]. ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 382 - +
[8] Simulation of silicon nanowire transistors using Boltzmann transport equation under relaxation time approximation
Jin, Seonghoon
Tang, Ting-Wei
Fischetti, Massimo V.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (03) : 727 - 736
[9] Modeling of surface-roughness scattering in ultrathin-body SOI MOSFETs
Jin, Seonghoon
Fischetti, Massimo V.
Tang, Ting-Wei
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (09) : 2191 - 2203
[10] SPATIAL VARIATION OF CURRENTS AND FIELDS DUE TO LOCALIZED SCATTERERS IN METALLIC CONDUCTION
LANDAUER, R
[J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1957, 1 (03) : 223 - 231

← 1 2 3 →