共 50 条
- [23] Optimizing Test Wrapper for Embedded Cores using TSV based 3D SOCs 2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 31 - 36
- [25] A Hierarchy Physical Design Technique for TSV-based 3D Integrated Circuits Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2023, 50 (08): : 134 - 140
- [29] Integration of CNT in TSV (≤5 μm) for 3D IC Application and Its Process Challenges 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
- [30] Novel LC Resonant Clocking for 3D IC Using TSV-Inductor and Capacitor 2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,