Analog Layout Generator for CMOS Circuits

被引：46

作者：

Yilmaz, Ender ^{[1
]}

Duendar, Guenhan ^{[2
]}

机构：

[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85281 USA

[2] Bogazici Univ, Dept Elect & Elect Engn, TR-34342 Istanbul, Turkey

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2009年 / 28卷 / 01期

关键词：

Analog design automation; automatic layout generation; CMOS analog integrated circuits; computer-aided engineering; integrated circuit layout; MATCHING PROPERTIES; DESIGN TOOL; PLACEMENT;

D O I：

10.1109/TCAD.2008.2009137

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present a new layout level automation tool for analog CMOS circuits, namely, analog layout generator (ALG). ALG is capable of generating individual or matched components as well as placement and routing. ALG takes performance considerations into account, optimizing the layout in each step. A distinguishing feature of the tool is primarily providing spectra of generation possibilities ranging from full custom to automatic generation. ALG is not only designed to work as a standalone tool but also implemented to be the final step of an analog automation How. The flow supports circuit level specification in addition to layout level user specifications, so that it can be integrated into an analog automation system. Another feature of ALG is its interaction with a layout adviser tool, namely, YASA. YASA performs sensitivity simulations using a spicelike simulator providing sensitivities of performance parameters with respect to circuit parameters.

引用

页码：32 / 45

页数：14

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