A Comprehensive Test Compression Scheme based on Precomputed Test Sets

被引：0

作者：

Tian, Zhijian ^{[1
]}

Zhao, Fayong ^{[1
]}

机构：

[1] Fuyang Normal Coll, Sch Phys & Elect Sci, Fuyang 236037, Peoples R China

来源：

PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION APPLICATIONS (ICCIA 2012) | 2012年

关键词：

Run-length code; run-length assignment symmetrical code; test data compression; ON-A-CHIP; POWER; VOLUME;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

To cope with increasingly rigorous challenges that large scale digital integrated circuit testing is confronted with, a comprehensive compression scheme consisting of test-bit rearrangement algorithm, run-length assignment strategy and symmetrical code is proposed. The presented test-bit rearrangement algorithm can fasten don't-care bits, 0s or 1s in every test pattern on one of its end to the greatest extent so as to lengthen end-run blocks and decrease number of short run-lengths. A dynamical don't-care assignment strategy based on run-lengths can be used to specify the remaining don't-care bits after the test-bit rearrangement, which can decrease run-length splitting and maximize length of run-lengths. The symmetrical code benefits from long run-lengths and only uses 2 4-bit short code words to identify end-run blocks almost as long as a test pattern, and hence the utilization ratio of code words can be heightened. The presented experiment results show that the proposed comprehensive scheme can obtain very higher data compression ratios than other compression ones published up to now, especially for large scale digital integrated circuits, and considerably decrease test power dissipations.

引用

页码：907 / 913

页数：7

共 15 条

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