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- [3] A Parallel Architecture for High Speed BLAST Using FPGA 2014 22nd Iranian Conference on Electrical Engineering (ICEE), 2014, : 57 - 61
- [4] FPGA implementation of high speed parallel architecture for block motion estimation 2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS, 2004, : 245 - 250
- [5] The Implementation of High Speed Parallel Timing Synchronization Algorithm Based on FPGA 2018 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION SOFTWARE AND NETWORKS (ICCSN), 2018, : 484 - 487
- [7] An improved MUSIC algorithm implemented with high-speed parallel optimization for FPGA 2006 7TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION AND EM THEORY, VOLS 1 AND 2, PROCEEDINGS, 2006, : 426 - 429
- [8] A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification 2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2009, : 24 - 31
- [9] FPGA IMPLEMENTATION OF HIGH SPEED VEDIC MULTIPLIER USING CSLA FOR PARALLEL FIR ARCHITECTURE 2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS), 2014,
- [10] A Novel High-Speed Parallel Scheme for Data Sorting Algorithm Based on FPGA PROCEEDINGS OF THE 2009 2ND INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOLS 1-9, 2009, : 3508 - +