An Improved Doherty Amplifier Using Cascaded Digital Predistortion and Digital Gate Voltage Enhancement

This paper describes algorithms used to improve linearity, efficiency, and peak power of a Doherty amplifier whose auxiliary transistor gate voltage is adjusted digitally as a function of the signal envelope. Two predistortion stages are used to compensate for high-order memoryless nonlinearities and low-order memory effects. The digital gate voltage waveform is a sigmoid function of the predistorted signal's envelope with two voltage limits corresponding to class C and AB bias levels. The instantaneous gate voltage is controlled by two adjustable parameters: a breakpoint and a slope. The parameters are adjusted to reduce the variance of the AM-AM curve of the power amplifier. The enhancement of the gate voltage at higher signal envelope levels increases the peak power and enhances improves the efficiency of the Doherty amplifier structure. The cascaded digital predistortion ensures sufficient linearity to keep the ACPR2 below -55 dBc.