A survey on dynamically reconfigurable processors

被引：43
作者：
Amano, Hideharu [1 ]
机构：
[1] Keio Univ, Dept Informat & Comp Sci, Yokohama, Kanagawa 2238522, Japan
来源：
IEICE TRANSACTIONS ON COMMUNICATIONS | 2006年 / E89B卷 / 12期
关键词：
dynamically reconfigurable processors;
D O I：
10.1093/ietcom/e89-b.12.3179
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Dynamically reconfigurable processors are consisting of an array of processing elements whose functions and interconnections can be dynamically changed. 9 commercial systems are picked up, and their array structures, processing elements and interconnection architectures are classified.
引用
收藏
页码：3179 / 3187
页数：9
相关论文
共 38 条
[1]  
ABE S, 2006, P COOL CHIPS, V9, P412
[2]   S5: The architecture and development flow of a software configurable processor [J].
Arnold, JM .
FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2005, :121-128
[3]  
AWASHIMA T, 2005, P INT S ADV REC SYST, P159
[4]  
DEHON A, 1996, P 4 CAN WORKSH FIELD, P47
[5]  
EBELING C, 2003, P FPL, P21
[6]  
FUJII T, 1999, P INT SOL STAT CIRC, P360
[7]  
FURTEK F, 2004, P FIELD PROGR LOG AP, P125
[8]  
Goldstein SC, 1999, CONF PROC INT SYMP C, P28, DOI [10.1145/307338.300982, 10.1109/ISCA.1999.765937]
[9]  
HASEGAWA Y, 2006, P FPT DEC, P163
[10]  
HASEGAWA Y, 2006, P REC ARCH WORKSH RA
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