CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects

被引:1
作者
Garcia, Jose C. [2 ]
Montiel-Nelson, Juan A. [2 ]
Nooshabadi, Saeid [1 ]
机构
[1] Gwangju Inst Sci & Technol, Dept Informat & Commun, Kwangju, South Korea
[2] Univ Las Palmas Gran Canaria, Inst Appl Microelect, Las Palmas Gran Canaria, Spain
关键词
Digital CMOS; Interconnect signaling; Bus drivers; Bus receivers; Level converters; Low energy; Low-voltage; Performance tradeoffs;
D O I
10.1016/j.mejo.2008.12.003
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy x delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver-receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0 V 0.13 mu m CMOS technology, for signal transmission along a wire-length of 10 mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy x delay. (C) 2009 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1571 / 1581
页数:11
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