Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling

被引：1

作者：

Huang, Wenjie ^{[1
]}

Tang, Weiguo ^{[2
]}

Chen, Junlin ^{[3
]}

Wang, Lei ^{[1
]}

机构：

[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06268 USA

[2] Broadcom Inc, Wireless Commun & Connect Div, San Jose, CA 95134 USA

[3] Unicore Commun Inc, Res & Dev Dept, Fremont, CA 94538 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 08期

基金：

美国国家科学基金会;

关键词：

Non-binary LDPC decoder; AMC-EMS; DRAM; refresh rate; error resilience; ARCHITECTURE;

D O I：

10.1109/TCSII.2018.2883713

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a low-power non-binary low density parity-check decoder design exploiting domain specific information for high-throughput wireless video communication applications. The proposed technique can dynamically scale the refresh rate of DRAM according to channel conditions as well as decoding states, hence to greatly reduce the DRAM power as well as the decoder power with lower refresh overhead. Evaluation results show that the proposed technique can achieve significant decoder power saving than conventional techniques.

引用

页码：1391 / 1395

页数：5

共 45 条

[1] Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM
Park, Youn Sung
Blaauw, David
Sylvester, Dennis
Zhang, Zhengya
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (03) : 783 - 794
[2] Low-Power Non-Binary LDPC Decoder Design via Adaptive Message Length Control Exploiting Domain-Specific Information
Wenjie Huang
Lei Wang
Journal of Signal Processing Systems, 2021, 93 : 11 - 23
[3] Low-Power Non-Binary LDPC Decoder Design via Adaptive Message Length Control Exploiting Domain-Specific Information
Huang, Wenjie
Wang, Lei
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2021, 93 (01): : 11 - 23
[4] Decoder Design for Non-binary LDPC Codes
Liu, Fei
Li, Haitao
2011 7TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING (WICOM), 2011,
[5] Low-Power LDPC Decoder Design Exploiting Memory Error Statistics
Chen, Junlin
Wang, Lei
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), 2015, : 171 - 176
[6] Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-Power Refresh
Gong, Young-Ho
Chung, Sung Woo
IEEE TRANSACTIONS ON COMPUTERS, 2016, 65 (05) : 1507 - 1517
[7] Gigabit Rate Low-Power LDPC Decoder
Pisek, Eran
Rajan, Dinesh
Cleveland, Joseph
2011 IEEE INFORMATION THEORY WORKSHOP (ITW), 2011,
[8] Energy Efficient Decoder Design for Non-binary LDPC Codes
Yasodha, T.
Jocobraglend, I.
Jeyanthi, K. Meena Alias
POWER ELECTRONICS AND RENEWABLE ENERGY SYSTEMS, 2015, 326 : 1497 - 1507
[9] Architecture of a low-complexity non-binary LDPC decoder
Voicila, Adrian
Declercq, David
Verdier, Francois
Fossorier, Marc
Urard, Pascal
2008 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 2008, : 197 - +
[10] A Design Scheme for the Improved Non-binary LDPC Coder-decoder
Gao, Jing-Peng
Kong, Wei-Yu
Song, Yi-Bing
2016 INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION SECURITY (CSIS 2016), 2016, : 724 - 730

← 1 2 3 4 5 →